Nowadays, semiconductor memories are used in various applications such as a main storage of a large computer, a personal computer, home appliances, and a cellular phone. As types of the semiconductor memories, a volatile dynamic random access memory (DRAM), a static random access memory (SRAM), a nonvolatile mask read only memory (Mask ROM), a flash electrically erasable programmable read only memory (EEPROM) (NAND-flash memory or NOR-flash memory), and the like are on the market. In particular, the SRAM can be manufactured in a standard Si process and is incorporated in nearly all system LSIs, although there is a slight difference in the inside.
In the SRAM, in general, one memory cell that stores 1-bit information includes six transistors in total. A PMOS transistor and an NMOS transistor are connected in series to each other to form a CMOS inverter. Outputs and inputs of a pair of the CMOS inverters are cross-coupled to each other to form a flip-flop (Andrei Pavlov et al., “CMOS SRAM Circuit Design and Parametric Test in Nano-Scaled Technologies”, Springer, ISBN 978-1-4020-8362-4).
In this memory cell, contrary relations are required for driving forces of the transistors during readout and during writing. This causes an increase in cell size. Further, compared with a normal logic circuit, an operation margin of the memory cell is small. When the memory cell is caused to perform a low-voltage operation, in some case, the memory cell malfunctions.
To solve such problems, there is proposed a system for adding two read-only transistors and forming a memory cell with eight transistors in total (Leland Chang et al., “Stable SRAM Cell Design for 32 nm Node Beyond,” VLSI Technology Symposium, pp 128-129, June, 2005). In this memory cell, there is no limitation on driving forces of the transistors during readout and only limitation during writing is applied to the memory cell. Therefore, limitation on the size of cell transistors decreases, the size of the cell transistors can be reduced, the operation margin is improved, and the low-voltage operation can be performed.